Voltage Regulator and Control Circuit and Method Therefor

ABSTRACT

The present invention discloses a voltage regulator, and a control circuit and a control method therefor. The method for controlling a voltage regulator comprises: receiving a dynamic voltage identification signal which instructs the voltage regulator to change its output voltage to a target voltage, and generating a compensation signal to shorten an interval for the output voltage of the voltage regulator to reach the target voltage.

CROSS REFERENCE

This application claims the benefit of U.S. Provisional Application No.61/358,592, filed on Jun. 25, 2010.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a voltage regulator, and a controlcircuit and a method for controlling the voltage regulator, inparticular to such voltage regulator, control circuit and method whereina compensation signal is generated to adjust the output voltage of thevoltage regulator according to a dynamic voltage identification (DVID)signal.

2. Description of Related Art

The major concept of dynamic voltage adjustment is to supply a variableoperation voltage to the system. When the system needs to process datain high speed, the voltage is increased to a higher level to enhance theprocessing speed of a digital signal processor or a microprocessor. Whenthe system does not need to process data in high speed or it is in astand-by mode, the voltage is decreased to a lower level by aninstruction from the system, such that unnecessary power consumption canbe saved. Thus, it is required for a voltage regulator supplying theoperation voltage to the system to be able to quickly adjust its outputvoltage so as to meet the requirement from the processor.

FIG. 1 shows a prior art voltage regulator supplying a dynamic voltageto a processor. The voltage regulator 10 comprises a control circuit 12and a power stage 14. The control circuit 12 controls the power stage14. The power stage 14 includes two power transistors (Q1, Q2) and aninductor L. The control circuit 12 generates control signals to controlthe operations of the transistors (Q1, Q2) according to the outputvoltage Vout or a feedback signal FB extracted from the output side Voutby a feedback circuit 20, an inductor current I_(L) through the inductorL, and a DVID signal instructed by a CPU (Central Processing Unit) 11,so as to transmit electrical power from the input side Vin to the outputside Vout. The inductor current I_(L) through the inductor L charges acapacitor C. The voltage across the capacitor C is the output voltageVout at the output side. The load current I_(LOAD) is outputted from theoutput side and supplied to the CPU 11.

The specification of the DVID signal is defined by Intel in itsspecification of the voltage regulator module (VRM), which includesinstructions for various voltages and corresponding slew rates. Forexample, the CPU 11 sends a DVID signal to request the output voltageVout to change from 0.5V to 0.8V by a slew rate of 10 mV/ps, and hence,the voltage regulator 10 needs to raise the output voltage Vout to 0.8Vwithin 30 μs (=(0.8−0.5)/0.01). Intel also lists the specification ofload line impedance in the specification, expressed by ΔVout/ΔI_(LOAD).For example, the load line impedance of the voltage regulator 10 is 1mohm, and ΔVout/ΔI_(LOAD) is possibly desired to be 1 mV/A. That is,when the output voltage Vout drops 10 mV, the load current I_(LOAD)increases 10 A. However, the conventional voltage regulator 10 onlydetects the inductor current I_(L), but does not detect the actual loadcurrent I_(LOAD) Because this requires disposing a power consumingdevice on the output path.

Referring to FIG. 2A, when the output voltage Vout of the voltageregulator 10 is at a stable status, the average of the inductor currentI_(L) is equal to the load current I_(LOAD), so in prior art concept,the average of the inductor current I_(L) can represent the load currentI_(LOAD). However, referring to FIG. 2B, when the voltage regulator 10increases the output voltage Vout from 0.5V to 0.8V in response to theDVID signal from the CPU 11, it increases the inductor current I_(L) tobe larger than the load current I_(LOAD) so as to charge the capacitor Cwith extra current, such that the output voltage Vout can be raised to adesired target. Meanwhile, the voltage regulator 10 detects the risinginductor current I_(L), so it mistakes the load current I_(LOAD) to beincreasing at the same speed as the increase of the inductor currentI_(L). However, according to the requirement of the load line impedance,the actual output voltage Vout unexpectedly drops (referred to as“droop”). Consequently, the actual output voltage Vout delays itsresponse to reach a higher level, that is, it gets to the target voltage0.8V later than the expected time point, so it cannot meet the slew raterequirement in specification of the DVID signal. On the contrary, if thedesired output voltage Vout needs to drop to 0.5V from 0.8V, anunexpected negative droop or boost occurs in the actual output voltage,and there is a similar delay in the response time of the actual voltageVout. Even though the load line impedance of the voltage regulator isassumed to be zero, because of the finite bandwidth of the feedback loopin the circuit, the response of the output voltage Vout is stilldelayed.

In view of above, the present invention overcomes the foregoingdrawbacks by providing a voltage regulator and a control circuit and amethod, wherein a compensation signal is generated to adjust the outputvoltage of the voltage regulator according to a dynamic voltageidentification (DVID) signal. Consequently, the response time of theactual voltage Vout is improved to solve the problem of the delayedresponse due to the droop or negative droop.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a voltage regulatorto improve the response time of the actual output voltage such that theproblem of the delayed response due to the droop or negative droop issolved.

An objective of the present invention is to provide a control circuit ofa voltage regulator.

An objective of the present invention is to provide a control method ofa voltage regulator.

To achieve the foregoing objectives, in one aspect, the presentinvention provides a voltage regulator, comprising: a power stageincluding at least one power transistor operating to convert an inputvoltage to an output voltage; a feedback control loop feedbackcontrolling the operation of the power transistor according to theoutput voltage or a feedback signal related to the output voltage; and acompensation signal generator receiving a dynamic voltage identification(DVID) signal, and when the DVID signal requests the output voltage tochange to a target voltage, the compensation signal generator generatinga compensation signal to shorten an interval for the output voltage toreach the target voltage.

In the foregoing voltage regulator, the feedback control loop preferablyincludes: an error amplifier generating an error amplification signalaccording to (a) the output voltage or the feedback signal related tothe output voltage and (b) a voltage signal determined by the DVIDsignal; and a pulse width modulation (PWM) comparator generating anoutput signal according to the error amplification signal and a rampsignal so as to directly or indirectly control the power transistor thepower stage; wherein the compensation signal is inputted to the feedbackcontrol loop in one of the following manners:

-   (1) the compensation signal being added to the feedback signal as an    input to an input terminal of the error amplifier;-   (2) the compensation signal being added to the voltage signal    determined by the DVID signal as an input to another input terminal    of the error amplifier;-   (3) the compensation signal being added to the error amplification    signal as an input to an input terminal of the PWM comparator; or-   (4) the compensation signal being added to the ramp signal as an    input to another input terminal of the PWM comparator.

In one of the embodiments, the compensation signal generator includes alookup table circuit which generates the compensation signal incorrespondence to the DVID signal.

In one of the embodiments, the compensation signal generator includes adetermination circuit generating a selection signal according to theDVID signal, and a converter converting a predetermined voltage to thecompensation signal according to the selection signal, wherein thepredetermined voltage is a constant, or is variable in correspondence toa different value of the DVID signal.

In another aspect, the present invention provides a control circuit forcontrolling a voltage regulator to convert an input voltage to an outputvoltage, the control circuit comprising: a error amplifier generating anerror amplification signal according to (a) the output voltage or afeedback signal related to the output voltage and (b) a voltage signaldetermined by a DVID signal; a pulse width modulation (PWM) comparatorgenerating an output signal according to the error amplification signaland a ramp signal so as to directly or indirectly control a conversionfrom the input voltage to the output voltage; and a compensation signalgenerator receiving the DVID signal, and when the DVID signal requeststhe output voltage to change to a target voltage, the compensationsignal generator generating a compensation signal to shorten an intervalfor the output voltage to reach the target voltage, wherein thecompensation signal is inputted in one of the following manners:

-   (1) the compensation signal being added to the feedback signal as an    input to an input terminal of the error amplifier;-   (2) the compensation signal being added to the voltage signal    determined by the DVID signal as an input to another input terminal    of the error amplifier;-   (3) the compensation signal being added to the error amplification    signal as an input to an input terminal of the PWM comparator; or-   (4) the compensation signal being added to the ramp signal as an    input to another input terminal of the PWM comparator.

In another aspect, the present invention provides a control method forcontrolling a voltage regulator to convert an input voltage to an outputvoltage, the control method comprising: providing a feedback controlloop feedback controlling a conversion from an input voltage to anoutput voltage according to the output voltage or a feedback signalrelated to the output voltage; receiving a dynamic voltageidentification (DVID) signal; and generating a compensation signal as aninput to the feedback control loop to shorten an interval for the outputvoltage to reach a target voltage when the DVID signal requests theoutput voltage to change to the target voltage.

The present invention can be applied to synchronous or asynchronous buckconverters, boost converters, inverting converters, and buck-boostconverters, operating for example in pulse width modulation mode orpulse frequency modulation mode.

The objectives, technical details, features, and effects of the presentinvention will be better understood with regard to the detaileddescription of the embodiments below, with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art voltage regulator supplying a dynamic voltageto a processor.

FIGS. 2A and 2B show the waveform diagrams of the output voltage Vout ofthe prior art voltage regulator.

FIG. 3 shows a flow chart, illustrating the control method of thepresent invention.

FIG. 4 shows an embodiment the voltage regulator of the presentinvention.

FIG. 5 shows a schematic diagram, illustrating the waveform of theoutput voltage of the voltage regulator according to the presentinvention.

FIGS. 6-8 show several other embodiments of the control circuit of thepresent invention.

FIGS. 9A-9B show two embodiments of the compensation signal generator ofthe present invention.

FIG. 10 shows an embodiment of the converter in FIG. 9B.

FIGS. 11A-11J show other types of the power stage of the voltageregulator.

FIG. 12 shows another embodiment of the voltage regulator of the presentinvention.

FIG. 13 shows an embodiment replacing the on-time generator of theembodiment in FIG. 12 with an off-time generator 65.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 shows a flow chart, illustrating the control method of thepresent invention. As shown in Step 31, a voltage regulator receives aDVID signal from a CPU. The signal instructs the voltage regulator tochange its output voltage. The check of Step 32 is executed next. Whenthe signal requests the output voltage to rise to a higher targetvoltage, the process goes to Step 33; when the signal requests theoutput voltage to drop to a lower target voltage, the process goes toStep 34. As shown in Steps 33 and 35, the voltage regulator generates afirst compensation signal to accelerate the rising speed of the outputvoltage such that the slew rate of the output voltage approaches thedesired slew rate requested by the specification of the DVID signal, andthus shortening an interval for the output voltage to reach the targetvalue. When the output voltage reaches the target value, the processstops in Step 37; otherwise, the process goes back to Step 33.

As shown in Steps 34 and 36, the voltage regulator generates a secondcompensation signal to accelerate the dropping speed of the outputvoltage such that the slew rate of the output voltage approaches thedesired slew rate requested by the specification of the DVID signal, andthus shortening an interval for the output voltage to reach the targetvalue. When the output voltage reaches the target value, the processstops in Step 38; otherwise, the process goes back to Step 34.

The foregoing control method can be embodied in various ways in avoltage regulator. For example, the first compensation signal and thesecond compensation signal can be used to directly or indirectly changethe on and/or off time of the power transistors (Q1 and Q2) so as toshorten the interval for the output voltage to reach the target value,and thus satisfying the requirement defined by the specification of theDVID signal. FIG. 4 shows an embodiment of the voltage regulator of thepresent invention. The voltage regulator is shown to be a synchronousbuck converter operating in pulse width modulation mode as an example.However, the present invention can be applied to synchronous orasynchronous buck power converters, boost power converters, invertingpower converters, and buck-boost power converters, operating for examplein pulse width modulation mode or pulse frequency modulation mode.Referring to FIG. 4, the voltage regulator 40 of this embodimentcomprises a control circuit 41 controlling the operation of the powertransistors (Q1, Q2) of the power stage 49 to convert electrical powerfrom the input side Vin to the output side Vout. The control circuit 41comprises an error amplifier 42, a PWM comparator 43, and a driver stage44, and further comprises a compensation signal generator 45, an adder46, and a digital to analog converter (DAC) 47. The compensation signalgenerator 45 and the DAC 47 both receive the DVID signal, wherein theDAC 47 outputs a voltage signal V_(DAC) corresponding to the DVIDsignal, and the compensation signal generator 45 generates acompensation signal according to the DVID signal. The compensationsignal can be a positive signal or a negative signal, depending on thedirection of the output voltage Vout to be changed toward. The adder 46adds the voltage signal V_(DAC) to the compensation signal, and outputsa sum signal as a reference signal to the error amplifier 42. Thefunction of the compensation signal is to accelerate the slew rate ofthe output voltage Vout. In prior art, only the voltage signal V_(DAC)is used as the reference signal, and the slew rate of the output voltageVout is not satisfactory. The error amplifier 42 compares the feedbacksignal FB with the sum signal to generate an error amplification signalComp. The PWM comparator 43 compares the error amplification signal Compwith the ramp signal Ramp to generate a duty signal Duty. The driverstage 44 drives the power transistors Q1 and Q2 according to the dutysignal Duty. The feedback circuit 48 includes two resisters R1 and R2connected to each other in series. One terminal of the resister R1 iscoupled to the output voltage Vout, and one terminal of the resister R2is coupled to ground. The feedback signal FB is a dividend voltageextracted from the resister R2.

FIG. 5 shows a schematic diagram, illustrating the waveform of theoutput voltage of the voltage regulator according to the presentinvention. During the period T1, the DVID signal requests the outputvoltage Vout to rise according a predetermined waveform. As described inthe above, the output voltage of the prior art voltage regulator has aserious droop problem, as shown by the waveform of the unmodified Voutin this figure. However, by applying the present invention to thevoltage regulator, the droop problem can be solved because thecompensation signal generator provides the compensation signal toimprove the slew rate of the output voltage Vout. Referring to thewaveform of the modified Vout in this figure, the slew rate of themodified Vout is much better than that of the unmodified Vout. Duringthe period T2, the DVID signal requests the output voltage Vout to dropaccording a predetermined waveform. As described in the above, theoutput voltage of the prior art voltage regulator has a serious negativedroop (insufficient drop) problem, as shown by the waveform of theunmodified Vout in this figure. However, by applying the presentinvention to the voltage regulator, the negative droop problem can besolved because the compensation signal generator provides thecompensation signal to improve the slew rate of the output voltage Vout.Referring to the waveform of the modified Vout in this figure, the slewrate of the modified Vout is much better than that of the unmodifiedVout.

What FIG. 4 shows is only one embodiment among many possible variations.The compensation signal can be fed to the control circuit 41 at otherproper nodes, as long as it can directly or indirectly change the onand/or off time of the transistors Q1 and Q2 to shorten an interval forthe output voltage of the voltage regulator to reach the target voltage.Any such circuits achieving such purpose by a compensation signal shouldbe included in the scope of the present invention. For example,referring to FIG. 6, the adder 46 can be moved to the output terminal ofthe error amplifier 42. That is, the compensation signal is added to theerror amplification signal Comp. Or, referring to FIG. 7, thecompensation signal can be added to the ramp signal Ramp. Moreover,referring to FIG. 8, the compensation signal can be added to thefeedback signal FB. Also, the DVID signal or the compensation signal canbe used to directly adjust the duty signal Duty.

The compensation signal generator 45 can be embodied in several manners.FIGS. 9A-9B show two embodiments of the compensation signal generator ofthe present invention. Referring to FIG. 9A, the compensation signal canbe generated in correspondence to the DVID signal by a lookup tablecircuit 451. Referring to FIG. 9B, the compensation signal circuit 45can include a determination circuit 452 which determines whether theoutput voltage Vout should be increased or decreased according to theDVID signal, and generates a selection signal Sel. According to theselection signal Sel, the converter 453 converts a predetermined voltageVset to a proper compensation signal. The predetermined voltage Vset maybe a constant, or may be variable in correspondence to a different valueof the DVID signal. One embodiment of the converter 453 is shown in FIG.10. The converter 453 includes a voltage to current converter 71,current mirrors (72, 73), a selection circuit 74 and a current tovoltage converter 75. The voltage to current converter 71 includes anoperation amplifier 711, a transistor 712, and a resistor Rset. Sincethe signal Vset is inputted to the positive input terminal of theoperation amplifier 711, the current through the resister Rset is equalto Vset/Rset. The current mirror 72 mirrors the current to generate apositive current of Vset/Rset, whereas the mirror 74 mirrors the currentto generate a negative current of −(Vset/Rset). The selection circuit 74determines whether to select the positive current or the negativecurrent according to the selection signal Sel. The current to voltageconverter 75 converts the output of the selection circuit 74 to avoltage signal and outputs the signal as the compensation signal. Theforegoing embodiments are just some examples among many possiblevariations. The scope of the present invention should include anycircuits which is able to generate the compensation signal according tothe DVID signal or other signals indicating that the output voltage isrequired to be changed (such as by detecting the variation of the outputvoltage Vout).

The power stage 49 is not limited to the synchronous buck power stageillustrated in the foregoing embodiments, and it may be a synchronous orasynchronous buck power stage, a boost power stage, an inverting powerstage, or a buck-boost power stage, as shown in FIGS. 11A-11J. Moreover,the power stage is not limited to operating in pulse width modulationmode as shown in the foregoing embodiments, but also can operate inother modes such as in pulse frequency modulation mode as exemplified inFIG. 12. Referring to FIG. 12, the voltage regulator 60 includes acontrol circuit 61 to control the power stage 49. The control circuit 61includes an error amplifier 42, a PWM comparator 43, an on timegenerator 64, and a driver stage 44, and furthermore, it includes acompensation signal generator 45, an adder 46, and a DAC 47. The adder46 adds the voltage signal V_(DAC) to the compensation signal, andoutputs an sum signal as a reference signal to the error amplifier 42.The error amplifier 42 compares the output voltage Vout with the sumsignal to generate an error amplification signal Comp. The PWMcomparator 43 compares the error amplification signal Comp with aninductor current sense signal (the inductor current sense signal alsohas a waveform and characteristics similar to a ramp signal, so it canbe deemed as a form of ramp signal), and the comparison result triggersthe on time generator 64 to generate a one-shot pulse with a constant ontime. The driver stage 44 drives the power transistors Q1 and Q2 tooperate according to the output signal of the on time generator 64. Insuch pulse frequency modulation mode, the compensation signal alsofunctions to accelerate the slew rate of the output voltage Vout.Similarly, the above configuration can be modified such that the outputof the compensation signal generator 45 is added to the negative inputterminal (added with the output voltage Vout) of the error amplifier 42,to the output of the error amplifier 42, or to the negative inputterminal (added with the inductor current sense signal) of the PWMcomparator 43. Moreover, the DVID signal or the compensation signal canbe used to directly adjust the on time generated by the on timegenerator 64.

The present invention has been described in considerable detail withreference to certain preferred embodiments thereof. It should beunderstood that the description is for illustrative purpose, not forlimiting the scope of the present invention. Those skilled in this artcan readily conceive variations and modifications within the spirit ofthe present invention. For example, the positive and negative terminalsof a comparator, an error amplifier, or an operation amplifier areinterchangeable. In all of the embodiments, a device or circuit whichdoes not affect the major functions of the signals, such as a switch,etc., can be added between two circuits illustrated to be directlyconnected with each other. Moreover, the on time generator 64 in theembodiment of FIG. 12 can be replaced with an off time generator 65 inFIG. 13; the circuit is still a voltage regulator operating in pulsefrequency modulation mode except that the constant on time is replacedwith the constant off time, but the present invention is stillapplicable. Thus, the present invention should cover all such and othermodifications and variations, which should be interpreted to fall withinthe scope of the following claims and their equivalents.

1. A voltage regulator, comprising: a power stage including at least onepower transistor operating to convert an input voltage to an outputvoltage; a feedback control loop feedback controlling the operation ofthe power transistor according to the output voltage or a feedbacksignal related to the output voltage; and a compensation signalgenerator receiving a dynamic voltage identification (DVID) signal, andwhen the DVID signal requests the output voltage to change to a targetvoltage, the compensation signal generator generating a compensationsignal to shorten an interval for the output voltage to reach the targetvoltage.
 2. The voltage regulator of claim 1, wherein the feedbackcontrol loop includes: an error amplifier generating an erroramplification signal according to (a) the output voltage or the feedbacksignal related to the output voltage and (b) a voltage signal determinedby the DVID signal; and a pulse width modulation (PWM) comparatorgenerating an output signal according to the error amplification signaland a ramp signal so as to directly or indirectly control the powertransistor the power stage; wherein the compensation signal is inputtedto the feedback control loop in one of the following manners: (1) thecompensation signal being added to the feedback signal as an input to aninput terminal of the error amplifier; (2) the compensation signal beingadded to the voltage signal determined by the DVID signal as an input toanother input terminal of the error amplifier; (3) the compensationsignal being added to the error amplification signal as an input to aninput terminal of the PWM comparator; or (4) the compensation signalbeing added to the ramp signal as an input to another input terminal ofthe PWM comparator.
 3. The voltage regulator of claim 2, wherein thefeedback control loop further includes a constant on-time generator or aconstant off-time generator which generates a constant on time or aconstant off time according to the output signal of the PWM comparatorto control the power transistor, wherein the ramp signal is obtained bydetecting an inductor current of the power stage.
 4. The voltageregulator of claim 1, wherein the compensation signal generator includesa lookup table circuit which generates the compensation signal incorrespondence to the DVID signal.
 5. The voltage regulator of claim 1,wherein the compensation signal generator includes a determinationcircuit generating a selection signal according to the DVID signal, anda converter converting a predetermined voltage to the compensationsignal according to the selection signal.
 6. The voltage regulator ofclaim 5, wherein the predetermined voltage is a constant, or is variablein correspondence to a different value of the DVID signal.
 7. Thevoltage regulator of claim 5, wherein the converter includes: a voltageto current converter generating a current according to the predeterminedvoltage; a first current mirror mirroring the current to generate apositive current; a second current mirror mirroring the current togenerate a negative current; a selection circuit selecting the positivecurrent or the negative current according to the selection signal; and acurrent to voltage converter converting the positive current or thenegative current to a positive or negative voltage signal as thecompensation signal according to the selection by the selection circuit.8. A control circuit for controlling a voltage regulator to convert aninput voltage to an output voltage, the control circuit comprising: aerror amplifier generating an error amplification signal according to(a) the output voltage or a feedback signal related to the outputvoltage and (b) a voltage signal determined by a DVID signal; a pulsewidth modulation (PWM) comparator generating an output signal accordingto the error amplification signal and a ramp signal so as to directly orindirectly control a conversion from the input voltage to the outputvoltage; and a compensation signal generator receiving the DVID signal,and when the DVID signal requests the output voltage to change to atarget voltage, the compensation signal generator generating acompensation signal to shorten an interval for the output voltage toreach the target voltage, wherein the compensation signal is inputted inone of the following manners: (1) the compensation signal being added tothe feedback signal as an input to an input terminal of the erroramplifier; (2) the compensation signal being added to the voltage signaldetermined by the DVID signal as an input to another input terminal ofthe error amplifier; (3) the compensation signal being added to theerror amplification signal as an input to an input terminal of the PWMcomparator; or (4) the compensation signal being added to the rampsignal as an input to another input terminal of the PWM comparator. 9.The control circuit of claim 8, further comprising a constant on-timegenerator or a constant off-time generator which generates a constant ontime or a constant off time according to the output signal of the PWMcomparator.
 10. The control circuit of claim 8, wherein the compensationsignal generator includes a lookup table circuit which generates thecompensation signal in correspondence to the DVID signal.
 11. Thecontrol circuit of claim 8, wherein the compensation signal generatorincludes a determination circuit generating a selection signal accordingto the DVID signal, and a converter converting a predetermined voltageto the compensation signal according to the selection signal.
 12. Thecontrol circuit of claim 11, wherein the predetermined voltage is aconstant, or is variable in correspondence to a different value of theDVID signal.
 13. The control circuit of claim 11, wherein the converterincludes: a voltage to current converter generating a current accordingto the predetermined voltage; a first current mirror mirroring thecurrent to generate a positive current; a second current mirrormirroring the current to generate a negative current; a selectioncircuit selecting the positive current or the negative current accordingto the selection signal; and a current to voltage converter convertingthe positive current or the negative current to a positive or negativevoltage signal as the compensation signal according to the selection bythe selection circuit.
 14. A control method for controlling a voltageregulator to convert an input voltage to an output voltage, the controlmethod comprising: providing a feedback control loop feedbackcontrolling a conversion from an input voltage to an output voltageaccording to the output voltage or a feedback signal related to theoutput voltage; receiving a dynamic voltage identification (DVID)signal; and generating a compensation signal as an input to the feedbackcontrol loop to shorten an interval for the output voltage to reach atarget voltage when the DVID signal requests the output voltage tochange to the target voltage.
 15. The control method of a voltageregulator of claim 14, wherein the feedback control loop includes: anerror amplifier generating an error amplification signal according to(a) the output voltage or the feedback signal related to the outputvoltage and (b) a voltage signal determined by the DVID signal; and apulse width modulation (PWM) comparator generating an output signalaccording to the error amplification signal and a ramp signal so as todirectly or indirectly control a conversion from the input voltage tothe output voltage; wherein the compensation signal is inputted to thefeedback control loop in one of the following manners: (1) thecompensation signal being added to the feedback signal as an input to aninput terminal of the error amplifier; (2) the compensation signal beingadded to the voltage signal determined by the DVID signal as an input toanother input terminal of the error amplifier; (3) the compensationsignal being added to the error amplification signal as an input to aninput terminal of the PWM comparator; or (4) the compensation signalbeing added to the ramp signal as an input to another input terminal ofthe PWM comparator.
 16. The control method of a voltage regulator ofclaim 14, wherein the step of generating the compensation signal as aninput to the feedback control loop includes: looking up a table togenerate the compensation signal in correspondence to the DVID signal.17. The control method of a voltage regulator of claim 14, wherein thestep of generating the compensation signal as an input to the feedbackcontrol loop includes: determining whether the output voltage should beincreased or decreased according to the DVID signal; generating acorresponding positive or negative current according to thedetermination; and converting the positive or negative current to apositive or negative voltage signal as the compensation signal.